1) Field of the Invention
The present invention relates to a technology for generating a test pattern for testing a test circuit provided in an integrated circuit that includes a plurality of scan chains and the test circuit that tests the scan chains.
2) Description of the Related Art
Testing techniques for detecting manufacturing process defects of integrated circuits such as LSIs are known. For example, when a test pattern is verified using a logic simulator, parallel simulation of scan shifts based on normal operation of scan shift is generally performed.
Japanese Patent Application Laid Open Publication No. 2002-236144 discloses a conventional testing device and testing method for testing integrated circuits. The testing device includes a pattern generator that is incorporated in the integrated circuit and generates a test pattern, a plurality of shift registers formed with sequential circuits in the integrated circuit, and a pattern corrector that corrects the test pattern generated using input from the outside and inputs the test pattern corrected to the shift registers.
The conventional testing device and testing method allows a highly-accurate test to be executed in a short time. Moreover, the test can be executed without imposing severe limitations on design and without requiring any expensive tester.
However, if the parallel simulation of scan shifts is not performed in a current large scale integrated circuit, it is impossible to verify the test pattern during practical executing time.
In the conventional testing device and testing method, a scan data input terminal that is provided at an external terminal in a design stage of the conventional technology is not connected directly to an external pin, which causes an operation test of the scan shift not to be executed.
A test circuit includes a large number of gates as compared with those in a test circuit based on scanning technique, which causes possible failures to increase. On the other hand, an Automatic Test Pattern Generation (ATPG) program is used for generating test patterns for a target circuit to be tested, but is not used for generating test patterns for a test circuit itself that represents the testing device. Therefore, reliability of test is reduced. Moreover, a means to detect a failure of the test circuit is not present in the conventional technique.